Apple员工提供内推,学IC、embedded systems、power的,就业机会别错过!

CMU ECE毕业的一位同学,热心在一亩三分地论坛里给大家提供美国Apple公司职位的内推。

啥是内推?英文叫internal referral,就是Apple/苹果公司有了新职位,公司员工在他们内部的job referral systems里输入你的信息、帮你投简历。

内推的好处是:1)公司一般都会优先处理自己员工提交的简历,处理的速度一般会比从外面投的快,2)公司的HR肯定会看一下内推投的简历,外面投进来的,未必会看。

以下是这次放出来的职位,Silicon Engineering Group。Warald看了一下职位,都是在Cupertino总部的,主要是IC的职位,Circuit Design, Verification/Test职位很多,embedded/Power的职位很少。

后面还会有更多关于嵌入式系统(Embedded Systems)、Power的职位放出来,敬请留意一亩三分地找工求职版的帖子:http://www.1point3acres.com/bbs/thread-36066-1-1.html 内推的联系方式,里面有。

你当然需要有一亩三分地的账户才能查看。作为留学生,要在美国找工作,如果没有一亩三分地的账户,你也太out了!

Apple的确喜欢招收有工作经验的人,下面这些职位里有些明确写了工作年数的要求,但是Warald仔细查看了这些职位的job description,发现给fresh graduates的职位还是有不少的,比如Signal Integrity Engineer、Silicon Validation Engineer – Embedded、Power Analysis/ Modeling Engineer、Formal Verification Engineer等,从BSEE、MSEE到PHD都可以申请,不卡工作年限。

机会难得,求职从速!!!

Silicon Engineering Group
Employee Referral Program
Timing (STA) Manager
Sr. Physical Design Engineer – PnR
Physical Design Engineer – STA
Physical Design Engineer – Timing Spice
Physical Design Engineer – PDV
Physical Design Methodology Engineer
Signal Integrity Engineer
Serdes PCS Design Engineer
IC Clock Design Engineer
Analog IP Engineer
Analog IP Validation Engineer
Design Verification Engineer
Silicon Validation-Debug/Triage Engineer
Silicon Validation Engineer – Linux
Formal Verification Engineer
Graphics Validation Engineer
Silicon Validation Engineer – Embedded
ASIC Design Engineer
Silicon Engineering Manager
VLSI Design Manager
Analog Chip Development Engineer
Sr. Product Engineer
CPU Implementation Lead Engineer
CPU Implementation Engineer
Sr. Circuit Design Engineer
Embedded Software QA Engineer
Soc Test Engineer
CPU Technical Mgr/Lead- Debug
CPU Design Verification Engineer
Design Verification
Functional Verification Engineer
Design Verification Software
Micro-Architect – Orlando
Micro-Architect – Cupertino
3D Graphics Micro-Architect
Power Analysis/ Modeling Engineer
Logic Implementation
Logic Design Engineer
Functional Verification Engineer – Cupertino
Functional Verification Engineer – Orlando
3D Graphics Functional Verification
Sr. CAD Engineer – Synthesis – Austin
Sr. CAD Engineer – Synthesis – Cupertino
License and Compute Administrator – Austin
License and Compute Administrator – Cupertino
Queue Developer and Performance Engineer
CAD Engineer – Infrastructure & Queueing
CAD – Physical Design Engineer
Sr. P&R CAD Physical Design Engineer
Sr. CAD Engineer – Design Verification – Austin
Sr. CAD Engineer – Design Verification – Cupertino
Sr. EDA CAD Engineer – Timing
CAD – STA

 

下面是几个职位的job description作为例子。

Signal Integrity Engineer
Req: 13696680, 26622649
Location: Cupertino
We are looking to hiring a Signal Integrity Engineer in a group at Apple that develops SOCs that will be used in
Apple mobile devices. You will be responsible for the PI and SI for Apple SOCs covering the span from package to
board.
Core Responsibilities:
The Signal Integrity Engineer needs to have extensive experience in mobile product board designs, SI expertise in
Serial links (such as DisplayPort) as well as parallel bus standards (such as LPDDR2 interface), and power integrity at
package level and as well as board level. Responsibilities includes:
• Work with package design group and board design group to simulate/characterize package and board PI and
propose and implement design guidelines and product specific design improvement
• SI simulation and characterization for all high speed parallel and serial interfaces and provide feedback to
package and board design group for improvement.
• Lab measurement and correlation to close the SI/PI simulation and validation loop
Qualifications:
The ideal candidate should have experience in the actual product package/board design and analysis, PI/SI
methodology development, and lab correlation/validation of the simulation results.
• 2+ years of experience
• Familiar with lab equipment, such as VNA, TDR, real-time scope, spectrum analyzer, and etc
• Deep knowledge in 3D/2D EM simulation tools and transmission line theory
• High-speed board and PCB design experience
• Team work and good communication skills
Education:
BSEE/MSEE is required, and Ph.D is preferred

 

Silicon Validation-Debug/Triage Engineer
Req: 25590448
Location: Cupertino
Imagine what you could do here. At Apple, great ideas have a way of becoming great products, services, and
customer experiences very quickly. Bring passion and dedication to your job and there’s no telling what you could
accomplish.
Do you thrive at the interface of hardware and software and love analyzing problems and root-causing complex
bugs that result from their interactions? A sort of jack-of-all-trades, are you part kernel hacker, part logic designer,
part lab junkie, and have people skills to boot? Come talk to us.
We are looking for superstars in the growing Silicon Validation Debug and Regressions (SiVal D&R) team. SiVal D&R
performs SoC bug triage, silicon characterization, and maintains test racks.
As a Silicon Validation Debug and Triage Engineer, you will lead debug and triage of SoC bugs in Silicon, FPGA and
Emulation environments.
Core Responsibilities:
• In your job as debug and triage lead, your goal is to quickly and effectively root-cause issues believed to be SoC
issues. To this end, you will harness and modify production and test software from other teams.
• You will work with experts from many teams to understand SoC and system behavior: iOS kernel/driver, Silicon
Validation IP test SW, Factory diagnostics, SoC architecture, SoC IP design and verification, FPGA Prototyping,
Systems Integration, board designers, etc.
• To process failed units from factory burn-in tests, you will enhance our automated triage process.
• Your success will be defined by the time to closure of SoC bugs (wherever the root cause may lie), the
throughput of bugs closed, the relationships you build, and the improvements you bring about to our test rack
and automated triaging methodologies.
Qualifications:
• C, assembly, system programming, scripting
• UNIX kernel and device driver programming
• Uniprocessor and multiprocessor computer architecture
• SoC architecture, some IP block knowledge
• SoC design cycle
• Lab measurement equipment (oscilloscope, logic analyzer, bus analyzer)
• Methodical and creative analysis skills
• Enjoy debugging
• People and communication skills
Education:
BSEE/MSEE or BSCE/MSCE is required

 

Formal Verification Engineer
Req: 26138794
Location: Cupertino
In this highly visible role, you will be at the center of a System-on-a-chip (SoC) design verification effort interfacing
with design, with a critical impact on getting high quality and bug-free functional products to millions of
customers quickly.
Core Responsibilities:
As a formal verification engineer owning the complete formal verification for single or multiple design blocks and
IP’s, you will be responsible for:
• Working with SOC and IP design teams to develop a formal micro-architecture specification
• Developing a comprehensive formal verification test plan
• Proving properties of the design, finding design bugs, and working closely with design teams to help improve
the micro-architecture
• Architecting novel and innovative solutions for verifying complex design micro-architectures
• Developing and implementing re-usable and optimized formal models and verification code base
Qualifications:
The ideal candidate will have the following experience:
• Advanced knowledge of SoC and CPU designs, VLSI, and digital logic design
• Developed formal property proofs on any RISC/CISC architectures
• Deep understanding of pipeline architectures, memory/DMA controllers, out-of-order and speculative instruction
execution hardware, bus interconnects, and cache coherence mechanisms
• Solid understanding of formal verification technologies and abstraction techniques
• Knowledge and experience in interpreting hardware specifications and using temporal logic assertion-based
languages such as SVA or PSL
• Experience in using EDA formal tools and experience in CAD tool development is a plus
• Proficiency in any scripting language such as TCL/Perl/etc… with excellent debugging skills
• Strong team player with excellent communication skills
• Passionate! about developing world-class formal verification solutions
Education:
BSEE/MSEE/Ph.D or CS is required

Graphics Validation Engineer
Req: 7192021
Location: Cupertino
Core Responsibilities:
• System level validation of high-performance embedded graphics sub-systems in silicon
• Develop low-level software to validate functionality, conformance, and performance of graphics subsystems.
• Bring-up and debug devices on new hardware platforms.
• Work with cross functional teams to support product requirements.
Qualifications:
• Strong software skills in C/C++.
• Experience with hardware accelerated 3D graphics environments
• Knowledge of OpenGL, OpenGL ES
• Embedded software experience is a must.
• Device driver experience a plus.
Education:
BS in CS or EE

Silicon Validation Engineer – Embedded
Req: 15623133
Location: Cupertino
The candidate will become part of our IP testing team responsible for writing tests covering various SoC functional
units such as encryption, cpus, and image processing.
Core Responsibilities:
• Porting CFE/boot-code/RTOS to new SoC and CPU architectures,
• Improving the low-level support provided in our debug environments to provide better support for writing
higher-level tests (e.g. scaler, jpeg),
• Implementing device libraries to aid in the portability of device drivers, bringing up low-level code on new SoCs.
• Work with other teams to support our common SoC and memory init code
• Desired: write linux drivers, write directed tests for IPs on the SoC.
Qualifications:
• Good C programmer
• Experienced and interested in writing code to test IO devices and/or functional units
• Familiar with boot code, low-level OS code, drivers, computer initialization, IO devices, SoC bringup, debuggers
• Familiar with SoC architecture
• Linux driver experience an asset
Education:
BS in CS or EE

Power Analysis/ Modeling Engineer
Req: 26622021
Location: Cupertino
In this highly visible role, you will be responsible for developing power analysis methodologies for low power
design and implementation.
Core Responsibilities:
• Define and drive implementation of state-of-the-art low power design methodologies.
• Work with design teams to set power efficiency goals, and lead the effort to support them and drive them to
achieve those goals.
• Define and implement metrics to help track the progress of improvements and to help identify power
inefficiencies in important use case workloads.
• Share low power best practices design principles amongst the design team, and automate these practices when
possible.
• Work with Power Analysis team to define and perform studies to help analyze and reduce power.
• Power optimization.
• Development of power analysis methodologies
• Development of power models and projection of power before implementation
• Post-RTL and post-route power measurements
Qualifications:
• Good understanding of concepts of power consumption, estimation, and low power design required
• Proficiency in scripting languages, such as Perl, Tcl, Python, or Make, is required.
• Familiar with power estimation tools, such as PrimeTime-PX, PowerArtist, PowerPro, or EPS, is a plus.
• Experience optimizing low power solutions in the mobile space.
• Understanding of power considerations at architectural, block and circuit levels.
• Experience in power estimation and modeling methodologies.
• Familiarity with general CPU, GPU architecture and micro-architecture and implementation flows.
Education:
MSEE/CE